mixed voltage logic families

Why the Function Name Tells You Almost Nothing Two boards, same schematic: a Low Power Dual 2-Input And Gate in both. One passes EMC with margin while the other resets itself every time a relay fires. The difference between them was a single letter in the part number — the logic family, not the logic function. Choosing between HC, HCT, LVC, AUP, or the CD4000B series is really a decision about four things: input threshold, propagation delay, drive current, and quiescent power. Get those right and the board behaves the way it was drawn. Get them wrong and you spend a week chasing an intermittent fault that the datasheet would have flagged in one line. The Five Parameters That Pick the Family for You Every family datasheet leads with the same five numbers. Reading them in this order keeps you out of trouble. Parameter What it decides Spread across common families Vcc operating rangeWhether the part runs from your rail at all0.8 V (AUP) to 18 V (CD4000B) Input thresholdWhether your driver can legally drive it0.7 × Vcc vs. fixed 2.0 V (TTL) Propagation delayTiming margin at your clock rate2.5 ns to 120 ns Output drive (IOH/IOL)Rise time into your trace capacitance±1 mA to ±32 mA Static and dynamic currentBattery life, thermal load0.5 µA to 40 µA static Family Comparison: The Numbers Side by Side Family Vcc range Typical tpd @ 3.3 V Output drive Static Icc (max) Cpd Input threshold AUP0.8–3.6 V4.5 ns±4 mA0.9 µA~4 pF0.7 × Vcc LVC1.65–5.5 V3.8 ns±24 mA10 µA~10 pF0.7 × Vcc, 5 V tolerant inputs LV1.0–5.5 V6 ns±6 mA20 µA~12 pFTTL levels at 3.3 V AHC / AHCT2.0–5.5 V5–6 ns±8 mA20 µA~11 pF0.7 × Vcc / 2.0 V TTL HC2.0–6.0 V8 ns±4 mA40 µA~20 pF0.7 × Vcc HCT4.5–5.5 V8 ns±4 mA40 µA~20 pF2.0 V (TTL) CD4000B3.0–18 V60 ns @ 10 V±1 mA——0.7 × Vcc At 3.3 V, AUP is the quietest and LVC is the strongest driver. Stepping up to AHC and HC buys a wider supply window at roughly double the delay and a much higher Cpd — and Cpd is what actually drains a battery in a switching design. Input Thresholds: Where Most Designs Quietly Fail VIH is the first number to check. A CMOS input in the HC family wants 0.7 × Vcc, which is 3.5 V on a 5 V rail. A 3.3 V output driving it sits below that threshold in the worst case, so the gate works on the bench in July and fails on the first cold morning. Input type VIH at 5.0 V VIH at 3.3 V Driven by a 3.3 V CMOS output? HC / AHC (0.7 × Vcc)3.5 V2.31 VNo at 5 V, yes at 3.3 V HCT / AHCT (fixed 2.0 V)2.0 Vn/a, 5 V familyYes LVC (0.7 × Vcc)3.5 V, inputs 5 V tolerant2.31 VYes AUP (0.7 × Vcc)n/a1.26 V at a 1.8 V railYes from 1.8 V logic CD4000B (0.7 × Vcc)3.5 V2.31 VNo at 5 V The working rule: any time a 3.3 V source meets a 5 V CMOS input, specify an HCT or AHCT part, or put an explicit translator in the path. A 2-input single supply translating AND gate solves the same problem inside a single package when two devices share one rail but not one threshold. Propagation Delay Tracks the Supply Rail Vcc 1.8 V 2.5 V 3.3 V 5.0 V tpd, typical7.5 ns5.0 ns3.8 ns2.5 ns Max clock, 5-gate chain at 25% of period6.7 MHz10 MHz13 MHz20 MHz Delay falls as Vcc rises, which is why a design that is comfortable at 3.3 V can fall apart when the same schematic is ported to a 1.8 V rail. Dynamic current is the other half of that trade, and it scales with the square of the rail. Vcc Dynamic power per gate at 10 MHz (Cpd 10 pF, CL 15 pF) 1.8 V0.8 mW 2.5 V1.6 mW 3.3 V2.7 mW 5.0 V6.3 mW 1.8 V0.8 mW 2.5 V1.6 mW 3.3 V2.7 mW 5.0 V6.3 mW Dropping a 5 V design to 1.8 V cuts switching power by roughly 7× at the same clock rate. Drive Strength and Switching Speed into Real Capacitance Edge rate is a function of output impedance and load capacitance: tr ≈ 2.2 × Rout × Cload. That single line explains most overshoot problems. Output drive Approx. Rout 5 pF 15 pF 30 pF 50 pF ±1 mA (CD4000B)~400 Ω4.4 ns13 ns26 ns44 ns ±4 mA (AUP, HC)~60 Ω0.7 ns2.0 ns4.0 ns6.6 ns ±8 mA (AHC)~35 Ω0.4 ns1.2 ns2.3 ns3.9 ns ±24 mA (LVC)~14 Ω0.2 ns0.5 ns0.9 ns1.5 ns A fast LVC output driving a long trace is the classic ringing case. Fitting a 22–33 Ω series resistor at the source slows the edge just enough to damp the reflection without eating your timing budget. Crossing a Voltage Boundary: Four Options, Ranked Method Components Practical speed Best fit 5 V-tolerant input + open-drain pull-up1 resistorSlow, µs rangeI2C-class buses Series resistor + clamp diode1 resistorModerateSlow signals into a tolerant input Single-supply translating gate1 IC20–50 Mbps, one direction3.3 V to 5 V on a shared rail Dedicated dual-supply translator1 IC50–100 Mbps, bidirectionalSPI, parallel buses, two rails Where a wired-AND bus is required, a Single 2-input And Gate (open drain) gives you the open-drain output without adding a discrete transistor and its pull-up network. The middle two options in the table are where designers get caught: both work in simulation, and both carry a condition that a scope will find for you. Selection Matrix by Design Need Design need Reach for Why Longest battery life on a coin cellAUPStatic current in the sub-µA range Driving a heavily loaded busLVC or LVT±24 mA to ±32 mA output drive Interfacing a legacy 5 V TTL peripheralHCT or AHCT2.0 V input threshold Bidirectional bus across two railsDual-supply translatorIndependent VDDA and VDDB Wide industrial supply, up to 18 VCD4000BOperates beyond standard logic rails Debouncing a mechanical inputSchmitt-trigger gateBuilt-in hysteresis Compressing a small BOMConfigurable multiple-function gateOne part covers several functions Release Checklist Before the BOM Freezes Confirm every input’s VIH against the worst-case VOH of whatever drives it, not the typical value. Check the Vcc range against the rail’s tolerance including ripple, not just the nominal voltage. Verify that a 5 V tolerant input applies in the state you are actually using. Run the timing budget at the lowest rail voltage the specification allows. Add up Cpd across every switching gate on a battery-powered design. Check output drive against real trace and fanout capacitance. Fit series termination on any fast net longer than a few centimeters. Confirm whether channel-to-channel skew matters for your bus. Verify ESD and latch-up ratings against the environment the board will actually see. Standard logic is the least glamorous line on the BOM. Picking the family on the function name alone is the shortcut that puts a board back into EMC testing a second time.