AiP74LVCH16245

The AiP74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (n ) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8V and 3.6V making the device suitable for low voltage translation between any of the following voltages:0.8V,1.2V,1.5V,1.8V,2.5V and 3.3V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on n causes the outputs to assume a high-impedance OFF-stateThe device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state.

The AiP74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (n ) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8V and 3.6V making the device suitable for low voltage translation between any of the following voltages:0.8V,1.2V,1.5V,1.8V,2.5V and 3.3V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on n causes the outputs to assume a high-impedance OFF-stateThe device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state.

The AiP74AVC16245 is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.

The AiP74AUP1G00 provides the single 2-input NAND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G00 provides the single 2-input NAND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G04 provides the single inverting buffer.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1GU04 provides the single unbuffered inverting gate.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G06 provides the single inverting buffer with open-drain output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G0832 provides the Boolean function: Y=(A×B)+C. The user can choose the logic fuctions OR, AND and AND-OR. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G09 provides the single 2-input AND gate with an open-drain output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G11 provides the single 3-input AND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G17 provides the single Schmitt trigger buffer.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G34 provides two low-power, low-voltage buffers. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G38 provides the single 2-input NAND gate with open-drain output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G57 provides configurable multiple functions. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G58 provides configurable multiple functions. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G79 provides the single positive-edge triggered D-type flip-flop. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G86 provides the single 2-input EXCLUSIVE-OR gate function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G132 provides the single 2-input NAND Schmitt trigger.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G332 provides a single 3-input OR gate. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP1G373 provides the single D-type transparent latch 3-state output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G00 provides the dual the dual 2-input AND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G02 provides a dual 2-input NOR function which accept standard input signals. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G04 provides two inverting buffers.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2GU04 provides two unbuffered inverting gates. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V

The AiP74AUP2G06 provides two inverting buffers with open-drain output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G0604 provides a single inverting buffer with open-drain output and a single inverter which accept standard input signals.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G07 provides two non-inverting buffer with open-drain output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G08 provides the dual the dual 2-input AND function.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G09 provides a dual 2-input AND gate with an open-drain output. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.

AiPLS0102 is a voltage level translator. The circuit supports bidirectional multi-voltage level translationin the range of 0.8V to 5V without direction control.

AiP2206 is a bidirectional IC-bus and SMBus voltage-level translator with an enableport and isoperational from 1.0V to 3.6V(Vreft1))and 1.8V to 5.5V(Vbis(ref2)).AiP2206 allows bidirectional voltage-level translation from IV to 5V without the use of direction pins.The low ON-state resistance of the switch allows connections to be made with minimal propagation delayWhen the enable port is high, the translator switch is on, and SCLI and SDAl are connected to SCL.2 andSDA2 respectively, allowing data transmission at both ends. When the enable port is low, the switch is offand the ports are high-impedance state. AiP2206 will isolate both sides when the device is disabled, and provides voltage-level translation whenenabled.AiP2206 can be used to run two buses, one is at 400kHz operating frequency and the other is at 100kHzoperating frequency. If these two buses are at different frequencies, the 100kHz bus must be isolated whenthe other bus is operating at 400kHz. If the controller runs at 400kHz, the maximum system operatingfrequency may be lower than 400kHz due to the delay of the translation.Like the standard 12C system, AiP2206 needs to provide logic high level for translation bus throughpull-up resistor. AiP2206 has a standard 12C bus open-collector configuration. The pull-up resistance isdetermined by the transmission rate of the system, but both ends of the translator must have pull-upresistors. This device mainly works in IC bus devices of standard mode, fast mode and fast mode Plus tocooperate with SMBus devices. The maximum frequency depends on the RC time constant, but it isgenerally allowed more than 2MHz When the SDAl or SDA2 port is low level, it is ON-state betweenSDAl and SDA2 and there is a small ON-state resistor. Assuming that the reference high level of thedevice at SDA2 is higher than the reference high level of the device at SDA1, the output voltage at SDA1will be limited to the voltage set by VREFI when the device at SDA2 outputs a high level. When thedevice at SDAl outputs a high level, SDA2 is pulled up by pul-up resistor to the high level set by thedrain pull-up power supply voltage (VpuD). This allows users to freely switch high and low levels withoutdirection control pins. The operating principle of SCL 1/SCL2 channel is the same as that of SDAl/SDA2channel. All the channels have the same electrical characteristics, and there is a slight deviation in voltage orpropagation delay from one side to the other. Symmetric manufacturing of switches is beneficial to solvethe voltage-level translation of split transistors. The translator provides excellent ESD protection for low-voltage devices, and at the same time, it protects devices lacking electrostatic protection.

AiPGTL2003 is a voltage level translator. The circuit supports bidirectional multi-voltage level translation in the range of 0.8V to 5V without direction control.

The AiPGTL2014 is a 4-bit GTL-LVTTL bidirectional transceiver. LVTTL is the typical COMS input/output; GTL parameters allow free configuration: the level input threshold is provided externally, the output is open leakage output, and the high level is provided by external pull-up resistor, which can meet a variety of GTL level requirements.

The AiP74HC/HCT4851 is 8-channel analog multiplexers/demultiplexers with three digital select inputs (S0 to S2), an active-LOW enable input (E—), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). The devices feature injection-current effect control, which has excellent value in automotive applications where voltages in excess of the supply voltage are common.

The AiP74HC/HCT4851 is 8-channel analog multiplexers/demultiplexers with three digital select inputs (S0 to S2), an active-LOW enable input (E—), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). The devices feature injection-current effect control, which has excellent value in automotive applications where voltages in excess of the supply voltage are common.

The AiP74HC/HCT48751 is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features three digital select inputs (S0, S1 and S2), eight independent inputs/outputs (Yn), a common input/output (Z) and a digital enable input (E—). When E—is HIGH, the switches are turned off.

The AiP74HC/HCT48751 is a single-pole octal-throw analog switch (SP8T) suitable for use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features three digital select inputs (S0, S1 and S2), eight independent inputs/outputs (Yn), a common input/output (Z) and a digital enable input (E—). When E—is HIGH, the switches are turned off.

The AiP74HC/HCT48752 is a dual single-pole quad-throw analog switch (2×SP4T) suitable for use in analog or digital 4:1 multiplexer/demultiplexer applications. Each switch features four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E—) and two digital select inputs (S0 and S1) are common to both switches. When E—is HIGH, the switches are turned off.

The AiP74HC/HCT48752 is a dual single-pole quad-throw analog switch (2×SP4T) suitable for use in analog or digital 4:1 multiplexer/demultiplexer applications. Each switch features four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E—) and two digital select inputs (S0 and S1) are common to both switches. When E—is HIGH, the switches are turned off.

The AiP74HC/HCT48753 is a triple single-pole double-throw analog switch (3×SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E—) is common to all switches. When E—is HIGH, the switches are turned off.

The AiP74HC/HCT48753 is a triple single-pole double-throw analog switch (3×SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E—) is common to all switches. When E—is HIGH, the switches are turned off.

The AiP74LV4051 is a low-voltage CMOS device and is pin and function compatible with the AiP74HC/HCT4051. The AiP74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z).

The AiP74LV4052 is a low-voltage CMOS device and is pin and function compatible with the AiP74HC/HCT4052.The AiP74LV4052 is a dual 4-channel analog multiplexer/demultiplexer with a common select logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logics include two digital select inputs (S0 and S1) and an active LOW enable input (E(—)). With E(—) LOW, one of the four switches is selected (low impedance ON-state) by S0 and S1. With E(—) HIGH, all switches are in the high impedance OFF-state, independent of S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (S0, S1 and E(—)). The VCC to GND ranges are 1.0V to 6.0V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC-VEE may not exceed 6.0V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

The AiP74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer.

The AiP74LV48751 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common  input/output (Z).

The AiP74LV48752 is a dual 4-channel analog multiplexer/demultiplexer with a common select logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logics include two digital select inputs (S0 and S1) and an active LOW enable input (E—). With E—LOW, one of the four switches is selected (low impedance ON-state) by S0 and S1. With E—HIGH, all switches are in the high impedance OFF-state, independent of S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (S0, S1 and E—). The VCC to GND ranges are 2.0V to 6.0V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between VCC as a positive limit. VCC may not exceed 6.0V.

The AiP74LV48753 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer.

The AiP74LVC1G66 provides one single pole, single-throw analog switch function. It has two input/output terminals (Y and Z) and an active HIGH enable input pin (E). When E is LOW, the analog switch is turned off. 

The AiP74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z).Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65V to 5.5V.

The CD4051 is an 8-channel analog multiplexer/demultiplexer with three address inputs (S1 to S3), an active LOW enable input (E(—)), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). The device contains eight bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y7) and the other side connected to a common input/output (Z). With E(—) LOW, one of the eight switches is selected (low-impedance ON-state) by S1 to S3. With E(—) HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. If break before make is needed, then it is necessary to use the enable input.VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3, and E(—)). The VDD to VSS range is 3V to 9V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 9V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4051H is an 8-channel analog multiplexer/demultiplexer with three address inputs (S1 to S3), an active LOW enable input (E(—)), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). The device contains eight bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y7) and the other side connected to a common input/output (Z). With E(—) LOW, one of the eight switches is selected (low-impedance ON-state) by S1 to S3. With E(—) HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. If break before make is needed, then it is necessary to use the enable input.VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3, and E(—)). The VDD to VSS range is 3V to 18V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 18V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4051HS is an 8-channel analog multiplexer/demultiplexer with three address inputs (S1 to S3), an active LOW enable input (E—), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z).The device contains eight bidirectional analog switches, each with one side connected to an independentinput/output (Y0 to Y7) and the other side connected to a common input/output (Z). With E—LOW, one ofthe eight switches is selected (low-impedance ON-state) by S1 to S3. With E—HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. If break before make is needed, then it is necessary to use the enable input.VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3, and E—). The VDD to VSS range is 3V to 18V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 18V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS(typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4052 is a dual 4-channel analogue multiplexer/demultiplexer with common channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logic includes two select inputs (S1 and S2) and an active LOW enable input (E(—)). Both multiplexers/demultiplexers contain four bidirectional analog switches, each with one side connected to an independent input/output (nY0 to nY3) and the other side connected to a common input/output (nZ). With E(—) LOW, one of the four switches is selected (low-impedance ON-state) by S1 and S2. With E(—) HIGH, all switches are in the high-impedance OFF-state, independent of S1 and S2. If break before make is needed, then it is necessary to use the enable input.VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2, and E(—)). The VDD to VSS range is 3V to 9V. The analog inputs/outputs (nY0 to nY3, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 9V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4052H is a dual 4-channel analogue multiplexer/demultiplexer with common channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logic includes two select inputs (S1 and S2) and an active LOW enable input (E(—)). Both multiplexers/demultiplexers contain four bidirectional analog switches, each with one side connected to an independent input/output (nY0 to nY3) and the other side connected to a common input/output (nZ). With E(—) LOW, one of the four switches is selected (low-impedance ON-state) by S1 and S2. With E(—) HIGH, all switches are in the high-impedance OFF-state, independent of S1 and S2. If break before make is needed, then it is necessary to use the enable input.VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2, and E(—)). The VDD to VSS range is 3V to 18V. The analog inputs/outputs (nY0 to nY3, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 18V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E(—)). A HIGH on E(—) causes all switches into the high-impedance OFF-state, independent of Sn.VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E(—)). The VDD to VSS range is 3V to 9V. The analog inputs/outputs (nY0, nY1, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 9V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4053H is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E(—)). A HIGH on E(—) causes all switches into the high-impedance OFF-state, independent of Sn.VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E(—)). The VDD to VSS range is 3V to 18V. The analog inputs/outputs (nY0, nY1, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD-VEE may not exceed 18V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches.

The CD4066 provides four single-pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off.The CD4066 is pin compatible with the CD4016 but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range.

The CD4066H provides four single-pole, single-throw analog switch functions. It operates over a recommended VDD power supply range of 3V to 18V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4094 is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH.Two serial outputs (QS1 and QS2) are available for cascading a number of CD4094 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading CD4094 devices when the clock has a slow rise time.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

AiP74CBTLV3125 is a 4-bit bus single-channel analog switch circuit. Each bit is controlled by the separate enable port (1OE—to 4OE—) and enable ports are all Schmitt designed. To ensure the high-impedance OFF-state during power-up or power-down, it is recommended that nOE—connect an external pull-up resistor to VCC. When the circuit is in power down state (VCC=0V), the control port and the switch port are in high resistance state, which can effectively prevent backflow and circuit damage.

AiP74CBTLV3126 is a 4-Bit bus switch circuit. Each bit is controlled by the separate enable port (1OE~4OE) and enable ports are all Schmitt design. To ensure the high-impedance OFF-state during power-up or power-down, it is recommended that nOE connect an external drop-down resistor to GND. When the circuit is in power down state (VCC=0V), the control port and the switch port are in high resistance state, which can effectively prevent backflow and circuit damage.

AiP74CBTLV3245 is an 8-bit bus switch with output enable. The circuit has a common enable control port (OE—), which is Schmitt designed. To ensure the high-impedance OFF-state during power-up or power-down, it is recommended that OE—connect an external pull-up resistor to VCC. When the circuit is in power down state (VCC=0V), the control port and the switch port are in high resistance state, which can effectively prevent backflow and circuit damage.

AiP74CBTLV3253 is a dual 1-of-4 multiplexer/demultiplexer. The circuit has two common selection ports (S0, S1) and two enable control ports (1OE , 2OE ). To ensure the high-impedance OFF-state during power up or power down, 1OE and 2OE should be tied toVcc through a pull-up resistor. This device is fully specified for partial power-down applications using IOFF. The IOFFcircuitry disables the output, preventing the damaging backflow current through thedevice when it is powered down.

AiP74CBTLV3257 is a 4-Bit 1-of-2 FET Multiplexer/Demultiplexer. The circuit has a common selection port (S) and an enable control port (OE(—)).To ensure the high-impedanceOFF-state during power upor power down, OE(—) should be tied to Vcc through apull-up resistor.This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

AiP74CBTLV3306 is a 2-bit bus switch. The circuit has a common enable control port (OE—), which is designed as a Schmitt trigger. To ensure the high-impedance OFF-state during power up or power down, OE—should be tied to VCC through a pull-up resistor. This device is fully specified for partial power-down applications using IOFF. The IOFFcircuitry disables the output, preventing the damaging backflow current through thedevice when it is powered down.

AiP74CBTLV3861 is a 10-bit bus switch with output enable. The circuit has a common enable control port (OE -), which is Schmitt designed. To ensure the high-impedance OFF-state during power-up or power-down, it is recommended that (OE -)  connect an external pull-up resistor to VCC. When the circuit is in power down state (VCC=0V), the control port and the switch port are in high resistance state, which can effectively prevent backflow and circuit damage.

AiP74CB3Q3245 is an 8-bit bus switch with output enable and charge pump. A built-in charge pump is used to increase the gate voltage of the NMOS pass transistor, enabling the circuit to transmit 5.5V switching signals when VCC=3.3V.

AiP74CB3Q3251 is a 1-of-8 multiplexer/demultiplexer with charge pump. The circuit has selection port (S0 to S2) and enable control port (OE -).A built-in charge pump is used to increase the gate voltage of the NMOS pass transistor, enabling the circuit to transmit 5.5V switching signals when VCC=3.3V.

AiP74CB3Q3253 is a dual 1-of-4 multiplexer/demultiplexer. The circuit has selection port (Sn) and enable control port (nOE—).A built-in charge pump is used to increase the gate voltage of the NMOS pass transistor, enabling the circuit to transmit 5.5V switching signals when VCC=3.3V.

AiP74CB3Q3257 is a 4-bit 1-of-2 multiplexer/demultiplexer. The circuit has common select port (S) and enable control port (OE—).A built-in charge pump is used to increase the gate voltage of the NMOS pass transistor, enabling the circuit to transmit 5.5V switching signals when VCC=3.3V.

AiP74CB3Q3245 is a dual bus switch with charge pump. A built-in charge pump is used to increase the gate voltage of the NMOS pass transistor, enabling the circuit to transmit 5.5V switching signals when VCC=3.3V.

The CD4011 is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4013 is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q(—)). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4015 is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter).

The CD4017 is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q(—)5-9), active HIGH and active LOW clock inputs (CP0, CP(—)1) and an overriding asynchronous master reset input (MR).The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP(—)1 is LOW or a HIGH-to-LOW transition at CP(—)1 while CP0 is HIGH.When cascading counters, the Q(—)5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0=Q(—)5-9=HIGH; Q1 to Q9=LOW) independent of the clock inputs (CP0, CP(—)1).Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4019 is a quad AND/OR select gate.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground).Unused inputs must be connected to VDD, VSS, or another input.

The CD4020 is a 14-stage binary counter with a clock input ( ), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13).It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4021 is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7).Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4023 provides the positive triple 3-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to GND (usually ground). Unused inputs must be connected to VDD, GND, or another input.

The CD4024 is a 7-stage binary ripple counter。

The CD4025 is a triple 3-input NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4026 is a CMOS decade.counter/divider.

The CD4027 is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q(—)). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4028 is a 4-bit BCD to decimal decoder, a 4-bit BCD to octal decoder with active LOW enable or an 8-output(Y0 to Y7) inverting demultiplexer.

The CD4030 is a quad 2-input EXCLUSIVE-OR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4042 is a quad clocked “D” latch. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4043 is a quad R/S latch with 3-state outputs with a common output enable input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input (1R to 4R) and an active HIGH 3-state output (1Q to 4Q).When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown in function table. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE does not affect the state of the latch. The high impedance off-state feature allows common bussing of the outputs.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4044 is a quad R/S latch with 3-state outputs.

CD4060 is a 14-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, REXT and CEXT), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset input (MR).The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13=LOW), independent of other input conditions.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4067 is a 16-channel analog multiplexer/demultiplexer with four address inputs (A0 to A3), an active LOW enable input (E—), sixteen independent inputs/outputs (Y0 to Y15) and a common input/output (Z). The device contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y15) and the other side connected to the common input/output (Z). With E—LOW, one of the sixteen switches is selected (low-impedance ON-state) by A0 to A3. All unselected switches are in the high-impedance OFF-state. With E—HIGH all switches are in the high-impedance OFF-state, independent of A0 to A3. The analog inputs/outputs (Y0 to Y15 and Z) can swing between VDDas a positive limit and VSS as a negative limit. VDD to VSS may not exceed 9V

The CD4068 is an 8-input And Gate/Nand Gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4070 is a quad 2-input EXCLUSIVE-OR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4071 is a quad 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4073 is a triple 3-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4075 provides the positive triple 3-input OR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to GND (usually ground). Unused inputs must be connected to VDD, GND, or another input.

The CD4076 are quad D-type register with 3-state outputs. It operates over a recommended VDD power supply range of 3V to 15V referenced to GND (usually ground). Unused inputs must be connected to VDD, GND, or another input.

The CD4078 is an 8-input Or Gate/Nor Gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4081 is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4082 is a dual 4-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4093 is a quad two-input NAND gate. Each input has a Schmitt trigger circuit.The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage (VT+) and the negative voltage (VT-) is defined as hysteresis voltage (VH).It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4094 is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH.Two serial outputs (QS1 and QS2) are available for cascading a number of CD4094 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading CD4094 devices when the clock has a slow rise time.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4099 8-bit addressable latch is a serial input, parallel output storage register that can perform a variety of functions.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground).Unused inputs must be connected to VDD, VSS, or another input.

The AiP74LV08 provides a quad 2-input AND function.

The AiP74LVC08 provides four 2-input AND gates. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with AiP74HC14 and AiP74HCT14. The AiP74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

The AiP74LVC14 provides six inverting buffers with Schmitt trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V applications.

The AiP74LVC17 provides six non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V applications.

The dual 4-input positive-AND gate is designed for 2V to 5.5V VCC operation.

The AiP74LV32 is a low-voltage CMOS device that is pin and function compatible with AiP74HC32 and AiP74HCT32. The AiP74LV32 provides a quad 2-input OR function.

The AiP74LVC32 provides four 2-input OR gates.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC74 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nS(—)D) and (nR(—)D) inputs, and complementary nQ and nQ(—) outputs.The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

The AiP74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible with AiP74HC125 and AiP74HCT125. The AiP74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE—). A HIGH at nOE—causes the outputs to assume a high-impedance OFF-state

The AiP74LVC125 consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that are controlled by the output enable input (nOE(—)). A HIGH at nOE(—)causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs.

The AiP74LV126 is a low-voltage Si-gate CMOS device that is pin and function compatible with AiP74HC/HCT126. The AiP74LV126 consists of four non-inverting buffers/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high impedance OFF-state.

The AiP74LVC126 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state.Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs.

The AiP74LVC132 provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V environment.

The AiP74LVC138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y(—)0 to Y(—)7) that are LOW when selected.There are three enable inputs: two active LOW (E(—)1 and E(—)2) and one active HIGH (E3). Every output will be HIGH unless E(—)1 and E(—)2 are LOW and E3 is HIGH.This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four AiP74LVC138 devices and one inverter. The AiP74LVC138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

The AiP74LVC139 is a dual 2-to-4 line decoder/demultiplexer.. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74HC/HCT21 provide the 4-input AND function. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74LVC157 is a quad 2-input multiplexer which select four bits of data from two sources under the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E(—)) is active LOW. When pin E(—) is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the AiP74LVC157. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator.It is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common.The device is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S.Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible with the AiP74HC164 and AiP74HCT164. The AiP74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

The AiP74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7 ) available from the last stage. Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall times.

The AiP74LVC240 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE（—） and 2OE（—）.A HIGH on nOE（—） causes the outputs to assume ahigh-impedance OFF-state.Inputs can be driven from either 3.3V or 5V devices. In 3-state operation, outputs can handle 5V.Thesefeatures allow the use of these devices as translators in a mixed 3.3V and 5V environment.

  The AiP74LVC244 is an octal non-inverting buffer/line driver with 3-state outputs.The 3-state outputs are controlled by the output enable inputs 1OE(—) and 2OE(—). A HIGH on nOE(—) causes the outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times.Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can handle 5V. These features allow the use of these devices as translators in a mixed 3.3 V and 5V environm.    

The AiP74LV245 is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE—)and send/receive (DIR) for direction control. A HIGH on OE—causes the outputs to assume ahigh-impedance OFF-state.

The AiP74LVC245 is a 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable(OE(—)) input for easy cascading and a send/receive (DIR) input for direction control. OE(—) controls the outputs so that the buses are effectively isolated.Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.

The AiP74LVCH245 is an 8-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The AiP74LVCH245 bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC273 consists of eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC373 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and3- state outputs for bus-oriented applications.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in amixed 3.3V and 5V environment.

The AiP74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LV541 is an 8-bit buffer/line driver with 3-state outputs. The device features two output enables(OE—1 and OE—2). A HIGH on OE—n causes the associated outputs to assume a high-impedance OFF-state.

The AiP74LVC541 is an octal non-inverting buffer/line driver with 5V tolerant inputs and outputs. The 3-state outputs are controlled by the output enable inputs OE(—)1 and OE(—)2.This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3V and 5V applications.

The AiP74LVC573 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable ( ) input are common to all internal latches.When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output changes each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.When  is LOW, the contents of the eight latches are available at the outputs. When  is HIGH, the outputs go to the high impedance OFF-state. Operation of the  input does not affect the state of the latches.Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3V or 5V applications.The AiP74LVC573 is functionally identical to the AiP74LVC373, but has a different pin arrangement.

The AiP74LVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS device and is pin and functionally compatible with the AiP74HC595 and AiP74HCT595. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial output (Q7S) for cascading the device. It is also provided with an asynchronous reset input MR— (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE—) is LOW.

The AiP74LVC4245 is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3V and 5V bus in a mixed 3V and 5V supply environment.The device features an output enable input (pin ) for easy cascading and a send/receive input (pin DIR) for direction control. Pin controls the outputs so that the buses are effectively isolated.In suspend mode, when VCC(A) is zero, there will be no current flow from one supply to the other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7V).VCC(A)VCC(B), except in suspend mode.

The AiP74LVC/LVCH16244 are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC/LVCH16244 are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC/LVCH16245 are 16-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features two output enable (n ) inputs for easy cascading and two send/receive (nDIR) inputs for direction control. n controls the outputs so that the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.The AiP74LVCH16245 bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

The AiP74LVC/LVCH16245 are 16-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features two output enable (n ) inputs for easy cascading and two send/receive (nDIR) inputs for direction control. n controls the outputs so that the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.The AiP74LVCH16245 bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

The AiP74LVC/LVCH16373 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (AiP74LVCH16373 only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable( ) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices.When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When  is LOW, the contents of the eight latches are available at the outputs. When  is HIGH, the outputs go to the high impedance OFF-state. Operation of the  input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

The AiP74LVC/LVCH16373 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (AiP74LVCH16373 only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable( ) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices.When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When  is LOW, the contents of the eight latches are available at the outputs. When  is HIGH, the outputs go to the high impedance OFF-state. Operation of the  input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

The AiP74LVC/LVCH162373 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (AiP74LVCH162373 only) for each latch and 3-state outputs for bus-oriented applications. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC/LVCH162373 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (AiP74LVCH162373 only) for each latch and 3-state outputs for bus-oriented applications. The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVC1T45; AiP74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH1T45 holds unused or floating data inputs at a valid logic level.

The AiP74LVC1T45; AiP74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH1T45 holds unused or floating data inputs at a valid logic level.

The AiP74LVC2T45; AiP74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two 2-bits input-output ports(nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH2T45 holds unused or floating data inputs at a valid logic level.

The AiP74LVC2T45; AiP74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two 2-bits input-output ports(nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH2T45 holds unused or floating data inputs at a valid logic level.

The AiP74LVC2T45; AiP74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two 2-bits input-output ports(nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH2T45 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH4T245 are 4-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver . It features four 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a output enable input (n ) and dual supply pins (VCC(A) and VCC(B)).Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins nAn, n and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (n ) can be used to disable the outputs so the buses are effectively isolated.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn port and nBn port are in the high-impedance OFF-state. Active bus hold circuitry in the AiP74LVCH4T245 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH4T774 is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input ( ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V). Pins An,  and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input ( ) can be used to disable the outputs so the buses are effectively isolated.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH4T774 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH4T774 is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input ( ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V). Pins An,  and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input ( ) can be used to disable the outputs so the buses are effectively isolated.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.Active bus hold circuitry in the AiP74LVCH4T774 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input ( ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins An,  and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input ( ) can be used to disable the outputs so the buses are effectively isolated.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the AiP74LVCH8T245 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input ( ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins An,  and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input ( ) can be used to disable the outputs so the buses are effectively isolated.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the AiP74LVCH8T245 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH16T245 are 16-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation.The device can be used as two 8-bit transceivers or as a 16-bit transceiver.It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (n ) and send/receive (nDIR) input for direction control.Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins nAn, n and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (n ) can be used to disable the outputs so the buses are effectively isolated.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn port and nBn port are in the high-impedance OFF-state. Active bus hold circuitry in the AiP74LVCH16T245 holds unused or floating data inputs at a valid logic level.

The AiP74LVC/LVCH16T245 are 16-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation.The device can be used as two 8-bit transceivers or as a 16-bit transceiver.It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (n ) and send/receive (nDIR) input for direction control.Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5.0V). Pins nAn, n and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (n ) can be used to disable the outputs so the buses are effectively isolated.The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn port and nBn port are in the high-impedance OFF-state. Active bus hold circuitry in the AiP74LVCH16T245 holds unused or floating data inputs at a valid logic level.

The AiP74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device,superior to most advanced CMOS compatible TTL families.The AiP74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3V and 5V bus in a mixed 3V and 5V supply environment.This device can be used as two 8-bit transceivers or one 16-bit transceiver.The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1 and 2 ), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, n and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7V). VCC(B)≥VCC(A) (except in suspend mode).

The AiP74ALVC/ALVCH162374 are 16-bit Edge-triggered D-type Flip-flop with 3-state outputs.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74ALVC/ALVCH162374 are 16-bit Edge-triggered D-type Flip-flop with 3-state outputs.The input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment.

The AiP74LVT244/LVTH244 is an octal buffer that is ideal for driving bus lines. The device features two output enables (1 , 2 ), each controlling four of the 3-state outputs.

The AiP74LVT244/LVTH244 is an octal buffer that is ideal for driving bus lines. The device features two output enables (1 , 2 ), each controlling four of the 3-state outputs.

The AiP74LVT245; AiP74LVTH245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. It features an output enable ( ) input for easy cascading and a direction (DIR) input for direction control.

This device is an octal buffer that is ideal for driving bus lines. The device features two output enables (1 , 2 ), each controlling four of the 3-state outputs.The AiP74LVT2244 is designed with series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters.

This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an output enable input ( ) for easy cascading and a direction input (DIR) for direction control.The AiP74LVT/LVTH2245 is designed with series resistance in both the HIGH state and LOW-state of the output. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers and transmitters.

The AiP74LVT16240; AiP74LVTH16240 is an inverting 16-bit buffer that is ideal for driving bus lines.

The AiP74LVT16244; AiP74LVTH16244 is a 16-bit buffer and line driver featuring non-inverting 3-state bus outputs. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The AiP74LVT16244; AiP74LVTH16244 is a 16-bit buffer and line driver featuring non-inverting 3-state bus outputs. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The AiP74LVT16245; AiP74LVTH16245 is a high-performance BiCMOS product designed for VCC operation at 3.3V.This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an output enable input (n ) for easy cascading and a direction input (nDIR) for direction control.

The AiP74LVT16245; AiP74LVTH16245 is a high-performance BiCMOS product designed for VCC operation at 3.3V.This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an output enable input (n ) for easy cascading and a direction input (nDIR) for direction control.

The AiP74LVT16373 is a high-performance BiCMOS product designed for VCC operation at 3.3V.This device is a 16-bit transparent D-type latch with non-inverting 3-state bus compatible outputs.The device can be used as two 8-bit latches or one 16-bit latch. When latch enable (LE) input is HIGH, the Q outputs follow the data (D) inputs. When latch enable is taken LOW, the Q outputs are latched at the levels of the D inputs one setup time prior to the HIGH-to-LOW transition.

The AiP74LVT16374; AiP74LVTH16374 are high performance BiCMOS products designed for VCC operation at 3.3V.This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic levels set up at the nDn inputs.

The AiP74LVT16374; AiP74LVTH16374 are high performance BiCMOS products designed for VCC operation at 3.3V.This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic levels set up at the nDn inputs.

  The AiP74ACT00 is quad 2-input nand gate

The AiP74AC02 is quad 2-input nor gate

The AiP74ACT02 is quad 2-input nor gate.

The AiP74AC04 provides six inverting buffers.

The AiP74ACT04 provides six inverting buffers.

Quad 2-Input And Gate

The AiP74ACT08 provides four 2-input AND gates.

The AiP74AC14 is a hex schmitt-trigger inverter.

The AiP74AC74 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock(nCP) inputs, set (nS—D) and (nR—D) inputs, and complementary nQ and nQ—outputs. The set and rest are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

The AiP74ACT74 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nS—D) and (nR—D) inputs, and complementary nQ and nQ—outputs. The set and rest are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

The AiP74ACT244 is octal buffer and driver with 3-state output

The AiP74ACT245 are octal bus transceivers with 3-state outputs.

The AiP74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

The AiP74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input(DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.The AiP74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

The AiP74AVC4T245 is an 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features four 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a output enable input (n ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). Pins nAn, n and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (n ) can be used to disable the outputs so the buses are effectively isolated.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state.

The AiP74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features two 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a output enable input (n ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). Pins nAn, n and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (n ) can be used to disable the outputs so the buses are effectively isolated.The AiP74AVCH4T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

The AiP74AVC4T774 is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input ( ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). Pins An,  and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input ( ) can be used to disable the outputs so the buses are effectively isolated.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

The AiP74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two 8-bit input-output ports (An and Bn), a direction control input (DIR), a output enable input ( ) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V,1.2V,1.5V,1.8V,2.5V and 3.3V).Pins An, and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input ( ) can be used to disable the outputs so the buses are effectively isolated.The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

The AiP74AVCH8T245 is a 8-bit, dual supply transceiver that enables bidirectional level translation. It features two 8-bit input-output ports (An and Bn), a direction control input (DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8V and 3.6V making the device suitable for translating between any of the low voltage nodes (0.8V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The AiP74AVCH8T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.