AiP74HC04

The AiP74HC/HCT194 is a 4-bit bidirectional universal shift register.

The AiP74HC/HCT196 is a presettable decade and binary counter. Output Q0 is connected to input CP1(—) for BCD count. Output Q3 is connected to input CP0(—) for bi-quinary count. In the counting modes, state changes are initiated by the falling edge of the clock.

The AiP74HC/HCT196 is a presettable decade and binary counter. Output Q0 is connected to input CP1(—) for BCD count. Output Q3 is connected to input CP0(—) for bi-quinary count. In the counting modes, state changes are initiated by the falling edge of the clock.

The AiP74HC/HCT240 is an 8-bit inverting buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE(—) and 2OE(—)), each controlling four of the 3-state outputs. A HIGH on nOE(—) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC

The AiP74HC/HCT240 is an 8-bit inverting buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE(—) and 2OE(—)), each controlling four of the 3-state outputs. A HIGH on nOE(—) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT241 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE(—) and 2OE), each controlling four of the 3-state outputs. A HIGH on 1OE(—) or LOW on 2OE causes the associated outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The AiP74HC/HCT241 device features reduced input threshold levels to allow interfacing to TTL logic levels.

The AiP74HC/HCT241 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE(—) and 2OE), each controlling four of the 3-state outputs. A HIGH on 1OE(—) or LOW on 2OE causes the associated outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The AiP74HC/HCT241 device features reduced input threshold levels to allow interfacing to TTL logic levels.

The AiP74HC/HCT243 are quad bus transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. They are designed for 4-line asynchronous 2-way data communications between data buses. The output enable inputs (OE(—)A and OEB) can be used to isolate the buses.

The AiP74HC/HCT243 are quad bus transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. They are designed for 4-line asynchronous 2-way data communications between data buses. The output enable inputs (OE(—)A and OEB) can be used to isolate the buses.

The AiP74HC/HCT244 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE(—) and 2OE(—)), each controlling four of the 3-state outputs. A HIGH on nOE(—) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT244 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE(—) and 2OE(—)), each controlling four of the 3-state outputs. A HIGH on nOE(—) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC245 is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE — ) and send/receive (DIR) for direction control. A HIGH on (OE —)causes the outputs to assume ahigh-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC

The AiP74HC/HCT247 feature active-low outputs designed for driving common-anode LEDs or incandescent indicators directly. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.

The AiP74HCT245 is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE — ) and send/receive (DIR) for direction control.

The AiP74HC/HCT248 feature active-low outputs designed for driving common-cathode LEDs or incandescent indicators directly. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.

The AiP74HC138 decodes three binary weighted address inputs(A0, A1 and A2) to eight mutually exclusive outputs (Y(—)0 to Y(—)7). 

The AiP74HC/HCT251 is an 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0 to S2) and an output enable input (OE(—)). The select inputs select one of the eight binary inputs and route it to the complementary outputs (Y and Y(—)). A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT138 decodes three binary weighted address inputs(A0, A1 and A2) to eight mutually exclusive outputs (Y(—)0 to Y(—)7). 

The AiP74HC/HCT251 is an 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0 to S2) and an output enable input (OE(—)). The select inputs select one of the eight binary inputs and route it to the complementary outputs (Y and Y(—)). A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT597 is an 8-bit shift register with input flip-flops

The AiP74HC/HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT597 is an 8-bit shift register with input flip-flops

The AiP74HC/HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC is a quad 2-input NOR gate. Inputs include clamp diodes. 

The AiP74HC/HCT266 contains four independent 2-input XNOR Gates with open-drain outputs

The AiP74HCT02 is a quad 2-input NOR gate. Inputs include clamp diodes. 

The AiP74HC/HCT266 contains four independent 2-input XNOR Gates with open-drain outputs

The AiP74HC166 is an 8-bit serial or parallel-in/serial-out shift register. 

The AiP74HC/HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR(—)) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR(—) forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiPHCT166 is an 8-bit serial or parallel-in/serial-out shift register.

The AiP74HC/HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR(—)) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR(—) forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

The AiP74HC/HCT279 is a quad RS latches

The AiP74HC123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

The AiP74HC/HCT279 is a quad RS latches

The AiP74HC125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE(—)). 

The AiP74HC/HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE(—)). 

The AiP74HC/HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. 

The AiP74HC/HCT283 adds two 4-bit binary words (An plus Bn) plus the incoming carry (CIN). The binary sum appears on the sum outputs (S1 to S4) and the out-going carry (COUT) according to the equation: CIN+(A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4)==S1+2S2+4S3+8S4+16COUT Where (+) = plus. Due to the symmetry of the binary add function, the AiP74HC/HCT283 can be used with either all active HIGH operands (positive logic) or all active LOW operands (negative logic). In case of all active LOW operands the results S1 to S4 and COUT should be interpreted also as active LOW. With active HIGH inputs, CIN must be held LOW when no carry in is intended. Interchanging inputs of equal weight does not affect the operation, thus CIN, A1, B1 can be assigned arbitrarily to pins 5, 6, 7, etc.

The AiP74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. 

The AiP74HC/HCT283 adds two 4-bit binary words (An plus Bn) plus the incoming carry (CIN). The binary sum appears on the sum outputs (S1 to S4) and the out-going carry (COUT) according to the equation: CIN+(A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4)==S1+2S2+4S3+8S4+16COUT Where (+) = plus. Due to the symmetry of the binary add function, the AiP74HC/HCT283 can be used with either all active HIGH operands (positive logic) or all active LOW operands (negative logic). In case of all active LOW operands the results S1 to S4 and COUT should be interpreted also as active LOW. With active HIGH inputs, CIN must be held LOW when no carry in is intended. Interchanging inputs of equal weight does not affect the operation, thus CIN, A1, B1 can be assigned arbitrarily to pins 5, 6, 7, etc.

The AiP74HC157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). 

The AiP74HC/HCT365 is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OE(—)n). A HIGH on OE(—)n causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). 

The AiP74HC/HCT365 is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OE(—)n). A HIGH on OE(—)n causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC164 is an 8-bit serial-in/parallel-out shift register. e AiP74HC/HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial dataThe AiP74HC/HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7).

The AiP74HC/HCT366 is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OE(—)n). A HIGH on OE(—)n causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

AiP74HCT164 is an 8-bit serial-in/parallel-out shift register.

The AiP74HC/HCT366 is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OE(—)n). A HIGH on OE(—)n causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC48 feature active-low outputs designed for driving common-anode LEDs or incandescent indicators directly. 

The AiP74HC/HCT367 is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE(—)). A HIGH on nOE(—) causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT367 is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE(—)). A HIGH on nOE(—) causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). 

The AiP74HC/HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE(—)) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HCT237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). 

The AiP74HC/HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE(—)) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

The AiP74HC/HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE(—)) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the flip-flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The AiP74HCT374 features reduced input threshold levels to allow interfacing to TTL logic levels.

The AiP74HC/HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

The AiP74HC/HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE(—)) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the flip-flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The AiP74HCT374 features reduced input threshold levels to allow interfacing to TTL logic levels.

The AiP74HC257 is a quad 2-input multiplexer with 3-state outputs. 

The AiP74HC/HCT393 is a dual 4-stage binary ripple counter.

The AiP74HC/HCT257 is a quad 2-input multiplexer with 3-state outputs.

The AiP74HC/HCT393 is a dual 4-stage binary ripple counter.

The AiP74HC/HCT540 is an 8-bit inverting buffer/line driver with 3-state outputs. The device features two output enables (OE(—)1 and OE(—)2). A HIGH on OE(—)n causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT540 is an 8-bit inverting buffer/line driver with 3-state outputs. The device features two output enables (OE(—)1 and OE(—)2). A HIGH on OE(—)n causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT541 is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE(—)1 and OE(—)2). A HIGH on OE(—)n causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT541 is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE(—)1 and OE(—)2). A HIGH on OE(—)n causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT563 is an 8-bit D-type transparent latch with 3-state inverting outputs. The device features latch enable (LE) and output enable (OE(—)) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT563 is an 8-bit D-type transparent latch with 3-state inverting outputs. The device features latch enable (LE) and output enable (OE(—)) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE(—)) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE(—)) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT574 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE(—)) inputs. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the flip-flops.

The AiP74HC/HCT574 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE(—)) inputs. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the flip-flops.

The AiP74HC589 device consists of an 8−bit storage latch which feeds parallel data to an 8−bit shift register.Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC594/74HCT594 is an 8-bit serial-in/serial or parallel-out shift register with a storage register.

The AiP74HC/HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR(—) input. A LOW on MR(—) will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE(—)) is LOW. A HIGH on OE(—) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(—) input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC1G126 and AiP74HCT1G126 is a non-inverting buffer/line driver with 3-state output.

The AiP74HC/HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT01 contains four independent 2-input NAND Gates with open-drain outputs.

The AiP74HC/HCT01 contains four independent 2-input NAND Gates with open-drain outputs.

The AiP74HC/HCT03 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT03 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT05 contains six inverters. The outputs of the AiP74HC/HCT05 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly.

The AiP74HC/HCT05 contains six inverters. The outputs of the AiP74HC/HCT05 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly.

The AiP74HC/HCT06 contains six inverters. The outputs of the AiP74HC/HCT06 are open-drain.The open-drain outputs require pull-up resistors to perform correctly.

The AiP74HC/HCT07 contains six buffers. The outputs of the AiP74HC/HCT07 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly.

The AiP74HC/HCT07 contains six buffers. The outputs of the AiP74HC/HCT07 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly.

The AiP74HC/HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT11 is a triple 3-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.Input levels: For AiP74HC11: CMOS level For AiP74HCT11: TTL level   Specified from -40℃ to +125℃   Packaging information: DIP14/SOP14/TSSOP14

The AiP74HC/HCT11 is a triple 3-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT13 provides two 4-input NAND gates with Schmitt-trigger inputs.

The AiP74HC/HCT13 provides two 4-input NAND gates with Schmitt-trigger inputs.

The AiP74HC/HCT14 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The AiP74HC/HCT14 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The AiP74HC/HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT21 provide the 4-input AND function. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT21 provide the 4-input AND function. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT42 is a one of ten BCD to decimal decoder. It accepts four BCD inputs (0A to 3A) and provides ten mutually exclusive outputs (0Y(—) to 9Y(—)). The logic design ensures that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The most significant input (3A) produces an useful inhibit function when the device is used as a 1-of-8 decoder. The 3A input can also be used as the data input in an 8-output demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT42 is a one of ten BCD to decimal decoder. It accepts four BCD inputs (0A to 3A) and provides ten mutually exclusive outputs (0Y(—) to 9Y(—)). The logic design ensures that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The most significant input (3A) produces an useful inhibit function when the device is used as a 1-of-8 decoder. The 3A input can also be used as the data input in an 8-output demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT47 feature active-low outputs designed for driving common-anode LEDs or incandescent indicators directly. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.

The AiP74HC/HCT73 is dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP(—)) and reset (nR(—)) inputs; also complementary Q and Q(—) outputs.

The AiP74HC/HCT73 is dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP(—)) and reset (nR(—)) inputs; also complementary Q and Q(—) outputs.

The AiP74HC/HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nS(—)D) and reset (nR(—)D) inputs, and complementary nQ and nQ(—) outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nS(—)D) and reset (nR(—)D) inputs, and complementary nQ and nQ(—) outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT76 is dual J-K Flip-Flops (with Preset and Clear)

The AiP74HC/HCT76 is dual J-K Flip-Flops (with Preset and Clear)

The AiP74HC/HCT85 is a 4-bit magnitude comparator that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. For proper compare operation the expander inputs (IA>B, IA=B and IA<B) to the least significant position must be connected as follows: IA<B=IA>B=LOW and IA=B=HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA>B, QA=B and QA

The AiP74HC/HCT85 is a 4-bit magnitude comparator that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. For proper compare operation the expander inputs (IA>B, IA=B and IA<B) to the least significant position must be connected as follows: IA<B=IA>B=LOW and IA=B=HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA>B, QA=B and QA

The AiP74HC/HCT86 is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT86 is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT86 is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT93 is a 4-bit binary ripple counter.

The AiP74HC/HCT93 is a 4-bit binary ripple counter.

The AiP74HC/HCT95 is a 4-bit Parallel Access Shift Register.

The AiP74HC/HCT95 is a 4-bit Parallel Access Shift Register.

The AiP74HC/HCT107 is dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP(—)) and reset (nR(—)) inputs; also complementary Q and Q(—) outputs.

The AiP74HC/HCT107 is dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP(—)) and reset (nR(—)) inputs; also complementary Q and Q(—) outputs.

The AiP74HC/HCT112 is a dual negative-edge triggered JK flip-flop.

The AiP74HC/HCT112 is a dual negative-edge triggered JK flip-flop.

The AiP74HC/HCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The AiP74HC/HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The AiP74HC/HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY(—)0 to nY(—)3). Each decoder features an enable input (nE(—)). When nE(—) is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY(—)0 to nY(—)3). Each decoder features an enable input (nE(—)). When nE(—) is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT145 is a BCD-to-decimal decoders/drivers.

The AiP74HC/HCT145 is a BCD-to-decimal decoders/drivers.

The AiP74HC/HCT147 9-input priority encoders accept data from nine active LOW inputs  The devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”.  The “zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

The AiP74HC/HCT147 9-input priority encoders accept data from nine active LOW inputs  The devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”.  The “zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

The AiP74HC/HCT148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level.

The AiP74HC/HCT148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level.

The AiP74HC/HCT151 are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0 to S2) and an enable input (E(—)). One of the eight binary inputs is selected by the select inputs and routed to the complementary outputs (Y and Y(—)). A HIGH on E(—) forces the output Y LOW and output Y(—) HIGH. Inputs also include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT151 are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0 to S2) and an enable input (E(—)). One of the eight binary inputs is selected by the select inputs and routed to the complementary outputs (Y and Y(—)). A HIGH on E(—) forces the output Y LOW and output Y(—) HIGH. Inputs also include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT153 is a dual 4-input multiplexer. The device features independent enable inputs (nE(—)) and common data select inputs (S0 and S1). For each multiplexer, the select inputs select one of the four binary inputs and routes it to the multiplexer output (nY). A HIGH on E(—) forces the corresponding multiplexer outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT153 is a dual 4-input multiplexer. The device features independent enable inputs (nE(—)) and common data select inputs (S0 and S1). For each multiplexer, the select inputs select one of the four binary inputs and routes it to the multiplexer output (nY). A HIGH on E(—) forces the corresponding multiplexer outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT154 is a 4-to-16 line decoder/demultiplexer

The AiP74HC/HCT154 is a 4-to-16 line decoder/demultiplexer

The AiP74HC/HCT156 is a dual 2-to-4 decoder/demultiplexer.

The AiP74HC/HCT156 is a dual 2-to-4 decoder/demultiplexer.

The AiP74HC/HCT160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE(—)) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR(—)) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE(—), CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP)) Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE(—)) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR(—)) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE(—), CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP)) Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE(—)) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR(—)) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE(—), CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP)) Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE(—)) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR(—)) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE(—), CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP)) Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE(—)) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR(—)) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE(—), CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula: fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP))

The AiP74HC/HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE(—)) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR(—)) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE(—), CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula: fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP))

The AiP74HC/HCT165 is 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q(—)7). When the parallel load input (PL(—)) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL(—) is HIGH data enters the register serially at DS. When the clock enable input (CE(—)) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE(—) will disable the CP input. Inputs are overvoltage tolerant to 15V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The AiP74HC/HCT165 is 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q(—)7). When the parallel load input (PL(—)) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL(—) is HIGH data enters the register serially at DS. When the clock enable input (CE(—)) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE(—) will disable the CP input. Inputs are overvoltage tolerant to 15V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The AiP74HC/HCT173 is a quad positive-edge triggered D-type flip-flop.Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT173 is a quad positive-edge triggered D-type flip-flop.Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The AiP74HC/HCT174 is a hex positive edge-triggered D-type flip-flop with individual data inputs (Dn) and outputs (Qn).

The AiP74HC/HCT174 is a hex positive edge-triggered D-type flip-flop with individual data inputs (Dn) and outputs (Qn).

The AiP74HC/HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and ).

The AiP74HC/HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and ).

The AiP74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

The AiP74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

The AiP74HC/HCT191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

The AiP74HC/HCT191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

The AiP74HC/HCT192 is a synchronous BCD up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL(—)).

The AiP74HC/HCT192 is a synchronous BCD up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL(—)).

The AiP74HC/HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down.

The AiP74HC/HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down.

The AiP74HC/HCT194 is a 4-bit bidirectional universal shift register.