banner
TTL level
| Picture | PN | Description | Voltage Range | Nr of pins | Package |
|---|---|---|---|---|---|
-17689780049F8BMGmSH5.jpg)
|
AiP74HCT191▲ | Presettable synchronous 4-bit binary up/down counter | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-1768977716SellPcncN8.jpg)
|
AiP74HCT190▲ | Presettable Synchronous BCD Decade Up/Down Counter | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-1768977401b4BU3LybKj.jpg)
|
AiP74HCT175▲ | Quad D-type flip-flop with reset; positive-edge trigger | TTL level | 16 | DIP16/SOP16/TSSOP16 |
-17689772222n7zqS5KzD.jpg)
|
AiP74HCT174▲ | Hex D Type Flip-Flop with Reset; Positive-EdgeTrigger | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-1768977041k028Fmbm9x.jpg)
|
AiP74HCT173▲ | Quad D-type flip-flop; positive-edge trigger (3-state) | 4.5 - 5.5 | 14 | DIP16/SOP16/TSSOP16 |
-1768976821ZTCvVi6WLg.jpg)
|
AiP74HCT165 | 8-bit parallel or serial-in/serial-out shift register; TTL enabled | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-1768976510rL2Otn1mKJ.jpg)
|
AiP74HCT163▲ | Presettable synchronous 4-bit binary counter; synchronous reset | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-1768976264cwql0khlwv.jpg)
|
AiP74HCT161 | Presettable synchronous 4-bit binary counter; asynchronous reset; TTL enabled | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-1768976043KcNUnBDRdL.jpg)
|
AiP74HCT160▲ | Presettable synchronous BCD decade counter; asynchronous reset | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
-17689758339Z0qOWHiT1.jpg)
|
AiP74HCT156▲ | Dual 2-to-4 Line Decoder/Demultiplexer | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
|
AiP74HCT154▲ | 4-to-16 Line Decoder/Demultiplexer | 4.5 - 5.5 | 24 | SOP24/SSOP24/TSSOP24/DHVQFN24 |
-1768974587lJr1pC5Ke7.jpg)
|
AiP74HCT153▲ | Dual 4-input multiplexer | 4.5 - 5.5 | 16 | DIP16/SOP16/TSSOP16 |
IPv6 network supported
leave a message
Language
